With the development of the electrical technology, a FET with high integrity and operation speed is required. As each technology nodes shrink, the dimensions of a FET and the thickness of its gate oxide, however, must be reduced and gate leakage could be more likely triggered by the reduced gate length.
In order to reduce gate leakage, high dielectric constant (high-k) gate insulator layers are used and the conventional polysilicon gate electrode is replaced with a metal gate (MG) electrode to improve the device performance as the feature sizes has being decreased.
The conventional technique for fabricating a metal gate transistor includes the following steps: Firstly a metal-oxide-semiconductor (MOS) transistor with a poly-silicon dummy gate electrode is formed. After the MOS transistor is completed, the dummy gate electrode will be removed by an etching process. Subsequently, a metal layer is deposited in the region where the dummy gate electrode was originally located, while a MG electrode of the metal gate transistor is formed.
However, removing the dummy gate and depositing the metal layer may conversely affect the integration of the metal gate transistor with other semiconductor devices. For example, a poly-silicon layer initially used to form the dummy gate electrode of the MOS transistor may be used to form an element layer of a passive device, such as an electric resistor. To avoid the poly-silicon element layer from damages resulted by the etching process; a photo-resist may be required to mask the poly-silicon element layer of the electrical resistor before the etching process for removing the dummy gate electrode is carried out, thereby a step height measured from the MG electrode of the metal gate transistor and the element layer of the electrical resistor may occur. Thus certain amount of metal resides may be remained on the peripheral area of the electrical resistor after the metal deposition and a subsequent metal contact formation is performed. Accordingly, device performance may deteriorate.
Therefore, it is necessary to provide an advanced semiconductor device and the fabrication method thereof to obviate the drawbacks and problems encountered from the prior art.